1. Field of the Invention
The invention generally relates to computer systems and in particular to computer systems incorporating a personal computer interface (PCI) bus, an input/output (I/O) subsystem and an input/output advanced programmable interrupt controller (APIC).
2. Description of Related Art
Many state of the art personal computer systems employ one or more PCI buses configured in accordance with protocols as established by the PCI special interest group. A PCI bus is a high performance, high bandwidth bus well suited for handling transference of data between a host processor bus and I/O devices such as asynchronous transfer mode (ATM) chips or small computer system interface (SCSI) interface chips.
An example of a computer system configured to incorporate PCI buses is set forth in FIG. 1. More specifically, FIG. 1 illustrates a computer system 10 having set of a host microprocessors 12, a host chipset 14 and an I/O subsystem 16. A primary PCI bus 18 interconnects the host chipset and the input/output subsystem. A secondary PCI bus 20 interconnects the I/O subsystem and a set of I/O devices 22 which may include the aforementioned SCSI chips, ATM chips, or other I/O devices. The host chipset is connected to the host processor by a host bus 24 which, typically, is not a PCI bus. With this arrangement, the host chipset provides a bridge between the host bus and the primary PCI bus. The I/O subsystem provides a bridge between the primary PCI bus and the secondary PCI bus. The I/O subsystem is provided, in part, to handle I/O operations which would otherwise need to be handled by the host processor. The I/O subsystem may include a core processor 26 and a memory 28 to facilitate I/O operations. Exemplary specific components which may be configured in accordance with the architecture of FIG. 1 are Pentium or Pentium Pro host processor chips, Triton or Orion host chipsets and i960 I/O subsystems incorporating one of the 80960 family of I/O co-processor chips. Each of the foregoing are components provided by Intel Corporation, the assignee of rights to the present application, and each component name is a trademark thereof.
By incorporating an I/O subsystem with a processor and memory and by utilizing PCI buses, high speed throughput of data is achieved between the I/O devices and the host chipset. Although such high speed data throughput is useful for many applications, computer systems arranged as in FIG. 1 are particularly useful as file servers. One disadvantage, however, of utilizing PCI buses is that the PCI protocol provides for only four interrupt lines. In FIG. 1, the four PCI interrupt lines are not separately shown but are part of primary bus 18 and secondary PCI bus 20. I/O subsystem 16 includes a PCI interrupt controller 30 which receives the PCI interrupts and routes the interrupts, as needed, into core processor 26 for further processing. For many applications, particularly file server applications, four PCI interrupts is insufficient. To partially remedy this problem, computer system 10 incorporates an I/O APIC 32 within the host chipset and a local APIC unit 34 within each host processor. Additional non-PCI interrupt lines 36 are connected directly from input ports of the I/O devices 22 to the I/O APIC of the host chipset. The I/O APIC of the host chipset communicates directly with the local APICs of the host processors over a dedicated 3-wire APIC bus 38. With this arrangement, interrupt signals generated by the I/O devices are routed directly to the I/O APIC of the host chipset which, in turn, converts the interrupts to APIC standard interupts for routing to the host processors over the APIC bus.
Thus, the use of an I/O APIC within the host chipset allows for additional interrupt signals to be accommodate beyond those provided by the PCI buses. The APIC architecture provides many additional features and advantages, particularly directed towards handling of interrupts within a multi-processor system. APIC is a proprietary interrupt processing technology provided by Intel Corporation. The APIC interrupt architecture is specified within the multiprocessor specification (MPS) document version 1.1 which available from Intel Corporation (Order No. 242016-003).
To handle interrupts, the I/O APIC includes a redirection table, several storage registers and various state machines. The state machine controls storage and processing of values within the redirection table and the various registers. Two of the registers of the I/O APIC, namely an APIC register select register and an APIC window register, are directly accessible by the local APICs of the host processors. Other registers of the I/O APIC are internally accessed by the I/O APIC only. The redirection table, the various registers and the values stored therein, as well as the operations performed by the state machines, are defined by the APIC specification. The redirection table, the registers, the state machines and any other necessary components of the I/O APIC are all formed within a single integrated chip which forms part of the host chipset.
Thus, by employing an APIC architecture, far more interrupts are accommodated than the four interrupts provided with PCI. Moreover, intelligent processing of the interrupts can be performed both within the I/O APIC and within the local APIC. As such, a computer system employing the aforementioned APIC architecture has significant advantages over a system merely using PCI interrupts. However, room for improvement remains. One problem with the arrangement of FIG. 1 is that individual interrupt lines must be connected directly from ports of the I/O devices to the I/O APIC within the motherboard of the computer system. Routing interrupt lines along the motherboard is difficult, particularly for state of the art computer systems wherein components may be required to run at 200 MHz. Another disadvantage of the architecture of FIG. 1 is that the I/O APIC is hard-wired in silicon and is therefore limited in flexibility. Hence, once configured, the I/O APIC cannot merely be reprogrammed to perform additional or different APIC functions. Moreover, because the I/O APIC is configured in silicon, there are significant practical constraints on the size of the redirection table incorporated therein. As a result, practical systems incorporating an I/O APIC often include a relatively small redirection table which lacks flexibility otherwise available with a larger redirection table.
In view of the foregoing, it would desirable to provide an improved APIC architecture, particularly one which does not require interrupt lines to be physically connected to the host chipset from the I/O device ports and which does not have the physical and practical limitations imposed by a hard-wired I/O APIC system.